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MA808
ADVANCE INFORMATION
DS3162-2.0
MA808
FRAME ALIGNER WITH OPTIONAL TIME SLOT ZERO RECEIVER
The MA808 Frame Aligner chip has been primarily designed for use in equipment operating at the CCITT standard of 2048 kbit/s tor 30 channel PCM data signals. The basic function of the device is to accept a 2048 kbit/s data signal, whose frame structure conforms to CCITT recommendation G732 and frame synchronously align it to a local exchange/system clock. The frame aligner operation is such that once a synchronisation sequence, as defined in CCITT recommendation G732, is received from a distant source synchronisation is established. Consequently the data stream is delayed such as to align it to the timing required at the local source. Once three successive sync. words are received containing errors, synchronisation is lost. The chip will remain out of sync. until the synchronising sequence is received. The device can also, when configured in the `enhanced mode' perform the additional function of time slot zero recovery. A number of facilities are also provided to simplify the testing of the device and associated system.
T1 RXI ALM R T2 TSZ RCK CK FRS LCK T3 VSS
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19
VDD T7 T6 T5 T4 NC NC NC M SA1 RXO2 RXO1
MA 808
18 17 16 15 14 13
DG24 DP24
Figure 1: Basic Mode pin connections - top view. M tied to VSS
FEATURES
s Fabricated in Low Power CMOS s Optional Time Slot Zero Receiver s Detection of Frame Alignment Signals for 30 Channel PCM Highways Operating at 2048 kbit/s in Accordance with CCITT Recommendations G732 s Delay Compensation and Clock Alignment between the Transmission Line system and the Exchange s Compensation of Phase Jitter, Meeting the Requirements of CCITT s Detection and Indication of Loss of Frame Alignment s Provision of a Signal for Generation of AIS s Slip Compensation s Chip Functional Test Facilities s TTL Compatible s Operating Power Consumption 75mW max. s Single + 5V Supply s High Latch-up Immunity s 256 kHz Clock Output
CCR RXI ALM ER SA TSZ RCK CK FRS LCK Q8N VSS
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19
VDD Q1S Q1N Q3N Q4N Q5N Q6N Q7N M SA1 RXO2 RXO1
MA 808
18 17 16 15 14 13
DG24 DP24
APPLICATIONS
s Digital Multiplex Equipment s Interfaces between PCM Line and Switching Systems s Concentrators
Figure 2: Enhanced Mode pin connections - top view. M tied to VDD
1
MA808
OPERATION IN BASIC MODE (M =VSS)
FRAME ALIGNMENT The remote non-return-to-zero (NRZ) binary PCM data stream (RXI) required to be aligned must be applied to the frame aligner along with a synchronous clock (RCK). A time slot zero impulse (TSZ) as shown in Fig. 5 is also required to define the start ot the frame of input data. A local clock (LCK) provides the timing from which the output data is clocked. Frame reset pulse (FRS) is the data output timing pulse. The MA808 aligns the 16th bit of the incoming data to this pulse, as shown in Fig. 5, and the two NRZ binary outputs RXO1 and RXO2 are produced. RXO1 is purely a retimed version of the input data. RXO2 has the third bit of all time slot zero locations of the input data inverted, thereby deliberately corrupting the frame sync. and the frame sync. verification words. Once synchronisation has been established FRS may be removed. If synchronisation is lost, FRS must be reapplied in order to permit resynchronisation to be established. SLIP COMPENSATION Small differences in frequency between the local and remote clocks (LCK and RCK) are compensated for by the repetition of the previous frame, (`slipping in') or the omission of one complete frame of data (`slipping out'). INPUT ALARMS Two input alarms (SA1 and ALM) are provided which will set data output(s) to an `all ones' condition. ALM sets only RXO2 and SA1 sets both RXO1 and RXO2 high (Fig. 6). TEST FEATURES The operation of the internal memory of the MA808 is continuously monitored by performing a check sum comparison of the input and output data signals RXI and RXO1. When an error is detected, the time slot zero words of RXO1 and RXO2 are set `high'. When a `low' is applied to test input T3, the outputs RXO1, RXO2 and CK are forced into a high impedance condition, thereby allowing associated circuitry to be tested independently of the MA808. Note that this facility is only available in the basic mode of operation. OPERATION IN ENHANCED MODE (M=VDD) When configured in the enhanced mode the chip performs time slot zero (TS0) recovery in addition to the frame alignment function. TS0 recovery may also be performed independently. FRAME ALIGNMENT The operation of frame alignment is essentially the same as the basic mode, except that the TSZ pulse is an output rather than an input, in accordance with the operation of the TS0 receiver, as shown in Fig. 7. The operation of the input alarms to set the output data `high' is the same as described in the basic mode (Fig. 6). TIME SLOT ZERO RECEIVER Two output signals (TSZ and CCR) are provided so that the time slot zero receiver may be used independently of the frame alignment function. CCR is a channel reset pulse (as shown in Fig. 7) which goes `low' for one RCK period following a sync. word (every alternate frame) when the device is in sync. When the device is out of sync. the reset pulse occurs after each time slot zero. The TS0 receiver accesses information contained within time slot zeros and processes it to offer the facilities of synchronisation alarm (SA), error output (ER) and time slot zero spare bits (Q1S, Q1N, Q3N-Q8N). SYNCHRONISATION ALARM (SA) SA indicates loss of sync. as shown in Fig. 8. With the frame aligner operating in sync., SA will be `low'. Following the receipt of 3 successive sync. words containing errors, SA will become active. SA will remain `high' until the correct synchronising sequence as defined in CCITT recommendations G732 has been received. ERROR OUTPUT (ER) A logic signal, ER, indicating errors in sync. words, is provided as shown in Fig. 8, from which an AIS alarm may be generated. ER is activated at the beginning of the second bit of time slot 1 two frames after the receipt of a sync. word containing errors. If successive sync. words contain errors, the signal will remain active. If synchronisation is lost, ER will remain active but will go `low' for one period of the remote clock during the second bit of time slot 1, two frames after the receipt of the last valid sync. word, as long as synchronisation is not regained at this time. If synchronisation is regained, ER will go `low' for the two frames following the sync. word which caused synchronisation to be regained. The signal indicating an error in the sync. word two frames prior to synchronisation being regained will be delayed by one further sync. frame period. Consequently, it may be concluded that all errors in sync. words are accounted for in this signal, hence error monitoring in accordance with CCITT recommendation G732.3.1.6.1 may be performed. TIME SLOT ZERO SPARE BITS The spare bits contained in both time slot zero words are converted from serial to parallel format (Q1N, Q3N-Q8N inc. and Q1 S) are shown in Fig. 9.
2
MA808
PIN DESCRIPTIONS - BASIC MODE
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Def. T1 RXI ALM R T2 TSZ RCK CK FRS LCK T3 VSS RXO1 RXO2 SA1 M NC NC NC T4 T5 T6 T7 VDD Function Test input Data input Alarm input Reset input Test input TSO input Clock input 256kHz output Timing input Clock input Test input Negative supply Data output Data output Set to all 1s input Mode input No connection No connection No connection Test input Test input Test output Test output Positive supply Description Active high. To be tied to logic low during normal operation. Recovered distant data input. A logic high on this input sets RXO2 to an all 1 s condition. `Low' resets the device tied `high' normally. Active low. To be tied to logic high during normal operation. Remote TS0 timing signal. Recovered distant clock in sync. with RXI. 256kHz square wave clock output synchronous with LCK. Data output timing pulse coincident with 16th bit of the local clock. Local clock input. Active low. To be tied to logic high during normal operation. Nominally 0V. Retimed data output to LCK. As RXO1 except that bit 3 of each TS0 word is inverted. A logic low sets RXO1 and RXO2 to an all 1s condition. Connected to Vss for basic mode operation. To be left O/C during normal operation. To be left O/C during normal operation. To be left O/C during normal operation. Active when clocked by LCK (pin 10). To be tied to logic low during normal operation. Active when clocked by RCK (pin 7). To be tied to logic low during normal operation. To be left O/C during normal operation. To be left O/C during normal operation. Nominally + 5V.
PIN DESCRIPTIONS - ENHANCED MODE
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Def. CCR RXI ALM ER SA TSZ RCK CK FRS LCK Q8N VSS RXO1 RXO2 SA1 M Q7N Q6N Q5N Q4N Q3N Q1 N Q1 S VDD Function Channel reset Data input Alarm input Error output Sync. alarm O/P TSO output Clock input 256kHz output Timing input Clock input Output signal Negative supply Data output Data output Set to all 1s input Mode input Output signal Output signal Output signal Output signal Output signal Output signal Output signal Positive supply Descrlption An output used to reset other devices within the system. Recovered distant data input. A logic high on this input sets RXO2 to an all 1 s condition. A TS0 word error is signalled when ER goes to logic high. Loss of sync. is signalled when SA goes to logic high. Remote TS0 output signal, (internally connected to the on-chip frame aligner). Recovered distant clock in sync. with RXI. 256kHz square wave clock output synchronous with LCK. Data output timing pulse coincident with 16th bit of the local clock. Local clock input. Signal corresponding to bit 8 of the TS0 sync. verification word. Nominally 0V Retimed data output to LCK As RXO1 except that bit 3 of each TS0 word is inverted. A logic low sets RXO1 and RXO2 to an all 1s condition. Connected to VDD for enhanced mode operation. Signal corresponding to bit 7 of the TS0 sync. verification word. Signal corresponding to bit 6 of the TS0 sync. verification word. Signal corresponding to bit 5 of the TS0 sync. verification word. Signal corresponding to bit 4 of the TS0 sync. verification word. Signal corresponding to bit 3 of the TS0 sync. verification word. Signal corresponding to bit 1 of the TS0 sync. verification word Signal corresponding to bit 1 of the TS0 sync. word. Nominally +5V.
3
MA808
R
LCK RCK TSZ FRS SA1 ALM
CONTROL LOGIC
R RCK T3
WRITE BIT COUNTER
READ BIT COUNTER
R LCK T3
R RCK UNALIGNED DATA INPUT RXI
R
SIPO RAM
R
PISO
LCK ALIGNED DATA INPUT RXO1 RXO2
LCK
T6 R RCK T2 T4 R T3
PARITY SIPO
PARITY
WRITE ADDRESS COUNTER
ADDRESS MULTIPLEXER
READ ADDRESS COUNTER
R T3
RANGE DETECTOR
CK
CONTROL LOGIC
R
LCK RCK TSZ FRS SA1 ALM
Figure 3: Frame aligner block diagram
CCR ER SA TSZ
RXI R RCK T1 T2 Q1S Q1N Q3N Q4N Q5N Q6N Q7N Q8N
RCK DECODER TIME SLOT ZERO TO PARALLEL CONVERTER
R RCK T2
SYNC COUNTER
SYNC WORD DETECTOR AND STATE CONTROL
R
RCK
T7
4
Figure 4: TSO receiver block diagram
MA808
RCK I/P
RXI I/P
X00110 11 X1XXXXXX
TS0S
TS1
TS2
TS30
TS31
TS0N
TSZ I/P
BIT NO. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
LCK I/P TS0 FRS I/P
16th BIT
TS1
1st BIT OF TIME SLOT 2
RXO1 O/P
X0011011
RXO2 O/P
X0111011
Figure 5: Timing diagram - basic mode: general operation of frame alignment
DATA I/P TSOS TSON TSOS TSON TSOS TSON TSOS TSON TSOS TSON TSOS TSON
SA1 I/P
ALM I/P
RXO1 O/P X00110011 X00110011 X00110011 X00110011 X00110011 X1XXXXXX X1XXXXXX X1XXXXXX X1XXXXXX X1XXXXXX
RXO2 O/P X00110011 X00110011 X1XXXXXX X00110011 X00110011 X1XXXXXX X1XXXXXX
X1XXXXXX
Figure 6: Timing diagram: protocol timings of the alarm signals
5
MA808
RCK I/P
RXI I/P
X00110 11 X1XXXXXX
TS0S
TS1
TS2
TS30
TS31
TS0N
TSZ O/P
CCR O/P
*
*N.B. This pulse is only present when the MA808 is out of sync
LCK I/P
BIT NO. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
TS0 FRS I/P
16th BIT
RXO1 O/P
X0011011 TS0S (RETIMED)
RXO2 O/P
X0111011
Figure 7: Timing diagram - enhanced mode: general operation of frame aligner
6
MA808
DATA I/P
TSOS N
S
N
S
N
S
N
S
N
S
N
S
N
S
N
S
N
S
N
S
N
S
N
S
N
S
N
S
N
S
DATA I/P
B A SA
E A
E A
E A
B
E A
B A
B A
B A
B A
B A
E A
B A
B A
B A
B
A = X1XXXXXX B = X0011011 E = Error
ER
RCK
DATA I/P TS0 SA TS1 TS0 TS1 TS0 TS1
ER
Figure 8: Timing diagram - enhanced mode: protocol timings of TSO receiver alarms
7
MA808
DATA I/P TS0S TS0N TS0S TS0N TS0S TS0N TS0S TS0N
RXI 00011011 01000001 10011011 11111110 10011011 01000000 00011011 01000000 00011011
Q1S
Q1N
Q3N
Q4N
Q5N
Q6N
Q7N
Q8N
Figure 9: Timing diagram - enhanced mode: protocol timings of the signal lines
8
MA808
RCK tHDD tSUD RXI tSUTSO tSPTSO TSZ tHDTSOH tHDTSOL
LCK tPD RXO1 AND RXO2 tPC
CK tSUR tHDR
FRS
ALL TIMING REFERENCE LEVELS = 1.6V
Figure 10: Timing diagram - basic and enhanced mode timing waveforms
9
MA808
RCK
tPCCR1
tPCCR2
CCR tPER
ER
tPSA
SA tPQ
Q OUTPUTS ALL TIMING REFERENCE LEVELS = 1.6V
Figure 11: Timing diagram
ELECTRICAL CHARACTERISTICS
These characteristics are guaranteed over the following conditions (unless otherwise stated) TAMB = + 25 C
DC CHARACTERISTICS
Characteristic Low level input voltage High level input voltage Low level input current High level input current Low level output voltage High level output voltage Output leakage current Dynamic supply current Static supply current Symbol Min. VIL VIH IIL IIH VOL VOH lOL IDDD IDDS 2.4 10 10 0.5 2.8 10 15 1 A mA mA Value Typ. Units Max. 0.8 V V A A V VDD = 4.75V VDD = 5.25V VIN = VSS. VDD = 5.25V VIN = VDD = 5.25V lOL = 2mA, VDD = 4.75V IOH = 0 2mA VDD = 4.75V VSS< VOUT< VDD, VDD = 5.25V Conditions
10
MA808
AC TIMING CHARACTERISTICS (REFER TO FIGS. 10 AND 11)
Characteristic Symbol Min. Set up time RXI to RCK (HL) Set up time TSZ to RCK (HL) Set up time FRS to LCK (HL) Data hold time wrt RCK (HL) TSZ (L) hold time wrt RCK (HL) TSZ(H) hold time wrt RCK (HL) FRS hold time wrt LCK (HL) Nominal frequency Propagation delay, LCK to RXO1 and RXO2 Propagation delay, LCK (HL) to CK Propagation delay, RCK (HL) to CCR (HL) Propagation delay, RCK (LH) to CCR (LH) Propagation delay, RCK (LH) to TSZ Propagation delay, RCK (LH) to ER Propagation delay, RCK (LH) to SA Propagation delay, RCK (LH) to Q8N-Q3N, Q1N and Q1S tSUD tSUTSO tSUR tHDD tHDTSOL tHDTSOH tHDR f tPD tPC tPCCR1 tPCCR2 tPTSO tPER tPSA tPQ 25 20 150 100 50 100 150 2.048 30 0 0 0 20 20 20 20 150 175 150 200 200 200 200 200 Value Typ. Units Max. ns ns ns ns ns ns ns MHz ns ns ns ns ns ns ns ns Conditions
Outputs loaded to10pF, fCLOCK=2.048MHz
ABSOLUTE MAXIMUM RATINGS
Supply voltage, VDD-VSS Voltage on any pin (VIN) (See note 1) Current through any pin (See note 1) Storage temperature Operating temperature range - 0.3 to + 7.0V VSS - 0.3V to VDD + 0.3V 20mA -55C to + 125C -10C to+55C
NOTES 1. Guaranteed no latch-up conditions. 2. Stresses above those listed in the Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions, or at any other condition above those indicated in the Electrical Characteristics, is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
11
MA808
HEADQUARTERS OPERATIONS GEC PLESSEY SEMICONDUCTORS Cheney Manor, Swindon, Wiltshire SN2 2QW, United Kingdom. Tel: (0793) 518000 Fax: (0793) 518411 GEC PLESSEY SEMICONDUCTORS P.O.Box 660017, 1500 Green Hills Road, Scotts Valley, California 95067-0017, United States of America. Tel (408) 438 2900 Fax: (408) 438 5576
CUSTOMER SERVICE CENTRES * FRANCE & BENELUX Les Ulis Cedex Tel: (1) 64 46 23 45 Fax: (1) 64 46 06 07 * GERMANY Munich Tel: (089) 3609 06-0 Fax : (089) 3609 06-55 * ITALY Milan Tel: (02) 66040867 Fax: (02) 66040993 * JAPAN Tokyo Tel: (3) 5276-5501 Fax: (3) 5276-5510 * NORTH AMERICA Integrated Circuits and Microwave Products, Scotts Valley, USA Tel (408) 438 2900 Fax: (408) 438 7023. Hybrid Products, Farmingdale, USA Tel (516) 293 8686 Fax: (516) 293 0061. * SOUTH EAST ASIA Singapore Tel: 2919291 Fax: 2916455 * SWEDEN Johanneshov Tel: 46 8 702 97 70 Fax: 46 8 640 47 36 * UK, EIRE, DENMARK, FINLAND & NORWAY Swindon Tel: (0793) 518510 Fax : (0793) 518582 These are supported by Agents and Distributors in major countries world-wide. (c) GEC Plessey Semiconductors 1993 Publication No. DS3162 Issue No. 2.0 August 1993
This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. The Company reserves the right to alter without prior knowledge the specification, design or price of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to the Company's conditions of sale, which are available on request.
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